1. Field of the Invention
The present invention is related to the field of fabricating semiconductor devices.
2. Background Art
As semiconductor devices are scaled into the submicron and sub-half micron regimes, interconnect contacts become increasingly important in the overall performance of the semiconductor devices. Further, it is necessary to reduce the number of metallization steps comprising critical lithographic operations to fabricate the semiconductor devices. Critical lithographic steps are those that have more critical dimensional tolerances than noncritical lithographic steps. Low sheet resistance values are important for interconnect materials in order to reduce propagation delays and minimize voltage drops along interconnects. It is particularly important to reduce propagation delays due to the resistance and capacitance of interconnects as devices are scaled into the submicron regime. For small feature designs comprising dense, high performance devices, propagation delays along interconnects may exceed gate switching delays in metal-oxide semiconductor (MOS) devices. Contacts coupling metal and polysilicon and active silicon areas increasingly affect the overall resistivity of interconnects as semiconductor devices are scaled down into the submicron and sub-half micron regimes.
Silicides are used to reduce the interconnect resistance of metal with polysilicon and active silicon areas, i.e., the gate and source/drain of MOS devices, respectively. Silicides are compounds formed from silicon and refractory metals that exhibit significantly lower resistance than the sheet resistances of polysilicon and shallow diffusions. Silicides are produced by reacting refractory metal with exposed active silicon areas and polysilicon areas. The silicide provides a much lower contact interface between metal and the active silicon and polysilicon areas than regular metal/polysilicon and metal/silicon interfaces.
Commonly, aluminum-copper (AlCu) is used in silicon technologies for metal interconnects because of its low resistivity. However, AlCu has a number of problems forming contacts with silicides including aluminum spiking and junction penetration, as is well-known in the art. Barrier layers are used to eliminate these problems by preventing silicon diffusion. To prevent barrier spiking, diffusion barrier layers are deposited on the silicide before metallization. Materials such as titanium-tungsten (TiW) are used as barrier layers over silicides in a contact region. However, the prior art is not able to efficiently fabricate a diffusion barrier layer on polysilicon, polysilicon bilayers, and/or monosilicon layers in the submicron/sub half-micron regime. The polysilicon bilayers are structures containing polysilicon and tungsten silicide (WSi.sub.2), for instance, as is well-known in the art. While polysilicon bilayers with WSi.sub.2 are described, it should be apparent to a person skilled in the art that other layers may also be used in combination with polysilicon. The barrier layers may then be subsequently deposited. Additionally, layers including aluminum, aluminum alloy, tungsten, etc., are deposited on top of the barrier layers.
FIG. 1 is a prior art diagram illustrating a MOS transistor including a polysilicon area after silicidation. The device comprises a source including a doped region 112 and silicide layer 114, a gate including polysilicon layer 118 and silicide layer 120, and a drain including a doped region 122 and silicide 124. The active regions 112 and 122 may be donor doped n+ or acceptor doped p+ for NMOS or PMOS devices. For example, in FIG. 1, the active silicon regions 112 and 122 are donor doped n+ regions. The polysilicon 118 is isolated from n+ regions 122 and 112 by spacers 116A and 116B. The oxide spacers 116A and 116B prevent silicide formation on the sides of polysilicon layer 118. The transistor is isolated from other semiconductor devices by field oxides 110 and 126.
After the polysilicon is patterned (see FIG. 1), the prior art begins by depositing an isolation layer using a dielectric on the polysilicon. The isolation layer is then patterned where metal (e.g., AlCu) is to contact polysilicon using a contact mask. FIG. 2 is a prior art diagram illustrating a contact aperture 220 formed in dielectric layer 202 for polysilicon layer 118 of FIG. 1. The diagram of FIG. 2 provides an expanded diagram of the gate region of FIG. 1 illustrating two dimensions of the three-dimensional contact aperture 220. The contact aperture 220 has depth H into the dielectric layer 202 and width W. Silicide layer 120 forms the bottom surface of the contact aperture 220. Contacts may be similarly formed on doped regions 112 and 122.
Once the contact aperture 220 is etched open into the isolation layer 202, the prior art sputter deposits a metal film 310 to form a barrier layer 302 in the submicron contact aperture 220. FIG. 3 is a prior art diagram illustrating the sputter deposition of metal film 310 to form barrier layer 302 on the silicide region 120 of polysilicon 118. As illustrated in FIG. 3, the metal film is deposited on dielectric layer 202 as well. Variations in the thickness of metal film 310, especially in the contact aperture 220, are described in detail below. Barrier layers may be similarly formed on doped regions 112 and 122.
FIG. 4 is a prior art diagram illustrating the subsequent deposition of AlCu metal 402 onto metal film 310 and into contact aperture 220. The AlCu metal 402 is deposited on the barrier layer 302 filling the contact aperture 220. As described above, the diffusion barrier layer 302 functions to reduce aluminum spiking and junction penetration between the AlCu metal 402 and the polysilicon layer 118. However, in submicron geometries of the contact aperture 220, a number of problems arise due to the dimensions of the contact aperture 220.
In the prior art, the barrier layer 302 is sputter deposited after the formation of the contact 220 (illustrated in FIG. 3). Thus, problems arise due to poor step coverage because the thickness H of the dielectric layer 202 remains constant (i.e., the depth H of the contact aperture 220 through the dielectric 202 is fixed) whereas the other dimensions of the contact are reduced (e.g., the width W of contact aperture is reduced) into the submicron regime.
FIG. 5A is a diagram illustrating a prior art disadvantage of sputter depositing metal film 310 in contact aperture 220 to form barrier layer 302 on silicide layer 120. The thickness of the metal film 310 sputter deposited within contact aperture 220 to form barrier layer 302 is adversely affected by the smaller geometry sizes of the contact aperture 220 with respect to the nominal thickness T of the metal fihn 310 on a flat surface (e.g., top surface of dielectric layer 202). This produces poor step coverage because the aspect ratio increases in the submicron regime. Consequently, it is difficult to produce a uniform barrier layer thickness by sputter depositing the metal film 310 in the contact aperture 220. As illustrated in FIG. 5A, the thickness T' of barrier layer 302 contacting silicide layer 120 bulges in the center of the contact aperture 220, i.e., at location W'/2. In contrast, the thickness T" of barrier layer 302 contacting silicide layer 120 near the sides of contact aperture 220 in the dielectric layer 202 narrows significantly. The step coverage is also affected by the slope of the dielectric layer walls and the shape of the contact aperture. Poor step coverage results in loss of barrier integrity, which is a severe reliability problem for metallization. The varying thickness of the barrier layer 302 causes the barrier layer 302 to be less effective preventing diffusion at thickness T" and produces an undesired increase in resistance at thickness T'.
For example, referring to FIG. 5A, a desired film thickness T of 1000 angstroms (.ANG.) for barrier layer 302 is deposited, as illustrated on the top surface of dielectric layer 202. However, due to poor step coverage, tile thickness T' of barrier layer 302 is equal to 1200 .ANG. in the center of the contact aperture 220 whereas the thickness T" at the edges of the contact aperture 220 pinches to 300 .ANG..
Further still, referring to FIG. 5B, sputter depositing the barrier layer 302 may effectively close-off the contact aperture 220 in the submicron regime, creating a void in the dielectric layer 202. This is caused by shadowing effects when the aperture 220 is too deep relative to its other dimensions.
Prior art methods have attempted to improve the integrity of the barrier layer 302 since barrier integrity is a major reliability problem for metallization.
In another prior art method, collimated sputtering is the used to improve barrier integrity into the submicron regime. Collimated sputtering results in sputtering efficiencies on the order of 10%-20% of those of conventional means, thereby posing a severe trade-off with throughput. However, even with this method, the prior art is unlikely to be able to maintain barrier integrity into the sub-half micron regime.
In yet another prior art method, chemical vapor deposition (CVD) is use to improve barrier integrity. However, CVD applications such as selective tungsten (W) require the sputter deposition of a nucleating seed layer for contact fill. The nucleating seed layer is necessary in order for the subsequent CVD tungsten layer to adhere to the silicide layer 120. Thus, this prior art method requires deposition of a nucleating seed layer having the disadvantages of a metal film discussed with reference to FIGS. 5A and 5B. Thus, this prior art method has severe problems in the submicron and sub-half micron regime as well. To circumvent this problem, the prior art attempts to deposit a CVD seed layer in the contact adding to the cost of the manufacturing sequence.
In addition to disadvantages in poor barrier layer integrity, the prior art requires extra metallization processing steps. Metallization is used to fabricate both global and local interconnects on semiconductor circuits. Global interconnects cover large distances on a semiconductor chip connecting widely separated regions, thereby requiring low resistivity to reduce voltage drops and propagation delay due to the long interconnect lengths. Local interconnects cover shorter distances between devices in a particular region of a semiconductor chip and, therefore, may have higher resistivity. Straps are short interconnects formed by metallization. Metallization is also used to form trim elements including fuses, as is well-known in the art.
In the prior art, a trim element (fuse), a higher resistivity local interconnect/strap, and a lower resistivity global interconnect are fabricated in two metallization levels separated by an inter-level dielectric. The prior art requires at least two separate metallization depositions and three lithographic operations. Thus, while a trim element (fuse), a higher resistivity local interconnect/strap, and a lower resistivity global interconnect have been fabricated in the prior art, the features have not been fabricated in the same metallization layer.
Thus, a number of disadvantages exist in the prior art. A disadvantage of the prior art is that the barrier integrity performance is poor into the submicron regime. The prior art methods for achieving barrier integrity into the submicron/sub-half micron regime require the purchase of new equipment or additional hardware for existing equipment.
Another disadvantage of the prior art for applications such as selective tungsten (W) is the deposition of a nucleating seed layer for contact fill. The prior art has severe problems in the submicron and sub-half micron regime.
A further disadvantage of prior art for fabricating trim elements, higher resistivity local interconnects/straps, and lower resistivity global interconnects is that these three features require lithographic performance at the limit of available technology on two levels. In addition, the prior art requires the use of an additional metallization/dielectric level. While the prior art uses one or at most two of these features in their technologies, all three features have not been provided in one metallization technology.